1. Field of the Invention
The present invention relates to a serial transceiver, and more particularly, to a high speed transceiver without using an external clock signal and a communication method used by the high speed transceiver.
2. Description of the Related Art
As various communication methods have been developed and widely used, the demand of users for multimedia increases. Accordingly, studies for transmitting a larger amount of data at a higher speed more stably and minimizing a hardware configuration needed for the transmission have been made.
In general, in order to increase a data rate, one is selected from among a parallel transmission method of increasing the number of channels and simultaneously transmitting a number of pieces of data and a serial transmission method of transmitting data at a high speed through a single channel, to maximize the functions. Here, the parallel transmission method has problems in that data skew which means time differences between data transmitted through difference channels may exist between the various transmission channels, and as the number of channels increases, hardware costs increase. Therefore, the serial data transmission method is employed as a standard for a high speed transceiver and has been widely used. Moreover, studies for configuring high speed serial communications in parallel have been carried out. Since a rate of data transceived in the serial data transceiver is very high, data uncertainty increases due to noise and channel bandwidths. In order to reduce the data transmission uncertainty, the receiver has to recover a clock to have a smaller amount of jitter to perform sampling on input data and has to maintain a phase relationship between the recovered clock and the input data at an optimal state so that a bit error ratio (BER) is minimized. Therefore, in the high speed serial communications, a role of a clock recovery circuit for re-arranging clock signals in an optimal state to enable the receiver to receive a clock and data from the transmitter and perform sampling on the input data, is very important.
A general high speed data transceiver is constructed to simultaneously transmit a reference clock signal for providing a synchronization reference for high speed transception data in order to transmit data from the transmitter to the receiver. However, in this method, in a case where data has to be transmitted for a long distance ranging several meters, due to skew between the data and the reference clock, the receiver may have problems in recovering data. In addition, in order to change the transmission speed, the conventional transceiver has to change a reference clock signal of the receiver according to the transmission speed. In addition, in order to control the operation speed of the receiver, the transceiver has to change a digital code.
In order to solve the aforementioned problems, U.S. Pat. No. 6,680,970 discloses statistical methods and systems for data rate detection for multi-speed embedded clock serial receivers to detect an edge of data. However, in this case, due to limitations of data edge detection, jitter of a recovered clock signal is higher than in a case of using a linear phase detector. Therefore, speed limitations occur, and error possibility increases.
For another method, U.S. Pat. No. 5,838,749 discloses a method and apparatus for extracting an embedded clock from a digital data signal. In this method and apparatus, a scheme for loading a clock supplier on a clock recovery circuit is used in order to solve the aforementioned problems. However, due to the loaded clock supplier, there are problems in that areas, costs, and power are increased.